1. Field of the Invention
The present invention relates to a communication system, and more particularly, to a communication system using multi-phase clock signals.
2. Description of the Related Art
A communication system includes a transmitter and a receiver. The transmitter samples data with a clock signal having a fixed period, and transmits the sampled data. The receiver receives the clock signal as well as the data from the transmitter.
As information technology has been developed, integration density and operation speed of a semiconductor memory device have increased. A single data rate dynamic random access memory (SDR DRAM) outputs data of one bit during one clock cycle, and a double data rate dynamic random access memory (DDR DRAM) outputs data of two bits during one clock cycle. A quad data rate dynamic random access memory (QDR DRAM) outputs data of four bits during one clock cycle, and an octal data rate dynamic random access memory (ODR DRAM) outputs data of eight bits during one clock cycle. The QDR DRAM and ODR DRAM sample data with a multi-phase clock signal.
In a memory system using multi-phase clock signals, it is difficult to control skew between a clock signal and data. For example, in a conventional QDR DRAM using a differential clock signal, when the skew between the clock signal and the data is caused by a difference between a path of the data and a path of the clock signal, a jitter noise of up to 6 unit intervals (UI) may occur if a phase-lock operation is performed only in a receiver. In a conventional ODR DRAM, when the skew between the clock signal and the data occurs, a jitter noise of up to 12 UI may occur if the phase-lock operation is performed only in the receiver. Furthermore, in the memory system using the multi-phase clock signals, if the phase-lock operation is performed only in a clock generator of the receiver to lock phases of the data and the clock signal, the clock signal should be delayed by a long delay time through phase interpolation, thereby increasing a size of the clock generator of the receiver and increasing a noise in the receiver.
FIG. 1 is a timing diagram illustrating a process of synchronizing data with multi-phase clock signals in a conventional communication system. Referring to FIG. 1, a transmitter synchronizes data DATA and a clock signal CLOCK with each other, and transfers the synchronized data and clock signal. A sampling clock signal CK_SP is generated by delaying the clock signal CLOCK by a first delay time tDL by a delay line of a clock generator included in a receiver. A phase-interpolated sampling clock signal CK_SP_PI is generated by interpolating a phase of the sampling clock signal CK_SP, and thus the phase-interpolated sampling clock signal CK_SP_PI is delayed by a second delay time tPI with respect to the sampling clock signal CK_SP. In FIG. 1, P0 represents a rising edge of a clock signal having a phase of 0 degrees among multi-phase clock signals, P90 represents a rising edge of a clock signal having a phase of 90 degrees among the multi-phase clock signals, P180 represents a rising edge of a clock signal having a phase of 180 degrees among the multi-phase clock signals, and P270 represents a rising edge of a clock signal having a phase of 270 degrees among the multi-phase clock signals. In FIG. 1, an asterisk (*) represents a noise position of data or a clock signal. A noise of the data DATA outputted from the transmitter and a noise of the clock signal CLOCK outputted from the transmitter occur simultaneously. However, a noise of the sampling clock signal CK_SP generated in the receiver occurs when the first delay time tDL elapses after the noise of the data DATA occurs. A noise of the phase-interpolated sampling clock signal CK_SP_PI occurs when a third delay time, which is the sum of the first delay time tDL and the second delay time tPI, elapses after the noise of the data DATA occurs. The sampling clock signal CK_SP must be delayed by at least 2 Unit Intervals (UI) by phase interpolation so that the rising edge P0 of the phase-interpolated sampling clock signal CK_SP_PI corresponds in time to a bit D1 of the data DATA.
If data are synchronized with multi-phase clock signals in a manner illustrated in FIG. 1, a large jitter noise occurs and a clock generator requires a long delay time for the described synchronization. Furthermore, a complex circuit, such as a register, is needed for phase interpolation, and a chip size of a semiconductor integrated circuit increases.